Main Project Status (05/20/2016 - 03:17:32) | |||
Project File: | YODA-ASG.xise | Parser Errors: | No Errors |
Module Name: | Main | Implementation State: | Synthesized (Stopped) |
Target Device: | xc6slx16-3csg324 |
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Product Version: | ISE 14.7 |
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Design Goal: | Balanced |
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Design Strategy: | Xilinx Default (unlocked) |
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Environment: | System Settings |
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Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | Fri May 20 03:17:22 2016 | 0 | 0 | 0 | |
Translation Report | Out of Date | Fri May 20 03:10:14 2016 | 0 | 0 | 1 Info (0 new) | |
Map Report | Out of Date | Fri May 20 03:12:27 2016 | 0 | 1 Warning (0 new) | 10 Infos (0 new) | |
Place and Route Report | Out of Date | Fri May 20 03:13:42 2016 | 0 | 12 Warnings (0 new) | 0 | |
Power Report | ||||||
Post-PAR Static Timing Report | Out of Date | Fri May 20 03:14:04 2016 | 0 | 0 | 3 Infos (0 new) | |
Bitgen Report | Out of Date | Fri May 20 03:00:28 2016 | 0 | 1 Warning (0 new) | 1 Info (0 new) |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
ISIM Simulator Log | Out of Date | Thu May 19 22:57:10 2016 | |
WebTalk Report | Out of Date | Fri May 20 03:00:29 2016 | |
WebTalk Log File | Out of Date | Fri May 20 03:00:40 2016 |