Debounce Project Status (04/19/2016 - 08:44:49)
Project File: YODA-ASG.xise Parser Errors: No Errors
Module Name: async_receiver Implementation State: Programming File Not Generated
Target Device: xc6slx16-3csg324
  • Errors:
 
Product Version:ISE 14.7
  • Warnings:
 
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 40 18,224 1%  
    Number used as Flip Flops 40      
    Number used as Latches 0      
    Number used as Latch-thrus 0      
    Number used as AND/OR logics 0      
Number of Slice LUTs 45 9,112 1%  
    Number used as logic 44 9,112 1%  
        Number using O6 output only 30      
        Number using O5 output only 7      
        Number using O5 and O6 7      
        Number used as ROM 0      
    Number used as Memory 1 2,176 1%  
        Number used as Dual Port RAM 0      
        Number used as Single Port RAM 0      
        Number used as Shift Register 1      
            Number using O6 output only 1      
            Number using O5 output only 0      
            Number using O5 and O6 0      
Number of occupied Slices 16 2,278 1%  
Number of MUXCYs used 16 4,556 1%  
Number of LUT Flip Flop pairs used 45      
    Number with an unused Flip Flop 7 45 15%  
    Number with an unused LUT 0 45 0%  
    Number of fully used LUT-FF pairs 38 45 84%  
    Number of unique control sets 4      
    Number of slice register sites lost
        to control set restrictions
15 18,224 1%  
Number of bonded IOBs 13 232 5%  
Number of RAMB16BWERs 0 32 0%  
Number of RAMB8BWERs 0 64 0%  
Number of BUFIO2/BUFIO2_2CLKs 0 32 0%  
Number of BUFIO2FB/BUFIO2FB_2CLKs 0 32 0%  
Number of BUFG/BUFGMUXs 1 16 6%  
    Number used as BUFGs 1      
    Number used as BUFGMUX 0      
Number of DCM/DCM_CLKGENs 0 4 0%  
Number of ILOGIC2/ISERDES2s 0 248 0%  
Number of IODELAY2/IODRP2/IODRP2_MCBs 0 248 0%  
Number of OLOGIC2/OSERDES2s 0 248 0%  
Number of BSCANs 0 4 0%  
Number of BUFHs 0 128 0%  
Number of BUFPLLs 0 8 0%  
Number of BUFPLL_MCBs 0 4 0%  
Number of DSP48A1s 0 32 0%  
Number of ICAPs 0 1 0%  
Number of MCBs 0 2 0%  
Number of PCILOGICSEs 0 2 0%  
Number of PLL_ADVs 0 2 0%  
Number of PMVs 0 1 0%  
Number of STARTUPs 0 1 0%  
Number of SUSPEND_SYNCs 0 1 0%  
Average Fanout of Non-Clock Nets 3.04      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentMon 18. Apr 14:31:00 2016   
Translation ReportCurrentMon 18. Apr 14:31:04 2016   
Map ReportCurrentMon 18. Apr 14:31:13 2016   
Place and Route ReportCurrentMon 18. Apr 14:31:20 2016   
CPLD Fitter Report (Text)     
Power Report     
Post-PAR Static Timing ReportCurrentMon 18. Apr 14:31:25 2016   
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentTue 19. Apr 08:44:44 2016
WebTalk Log FileCurrentTue 19. Apr 08:44:48 2016

Date Generated: 04/19/2016 - 08:44:49